Conventionally, delayering methods in semiconductor and integrated circuit metrology and failure analysis include laborious, repetitive, and arguably blind polishing steps by general mechanical or RIE-polishing, followed by meticulous SEM inspection in between such steps. The average time for a single sample with an advanced minimum line width is on the order of 8-12 hours, meaning that at most, one machine can process 1 sample/day.
Various ion beam machining techniques are applicable to different end results. For example, a focused ion beam (FIB) can be used to cross-section a sample and/or to mill an area in the sample with nanometer-level precision. Beam currents in FIB tend to be in the range of 0.001-10 nA. FIB offers high beam precision and excellent target alignment capability. Plasma-FIB (PFIB) can be used for normal milling, and is applicable over a wide range of conditions. For example, PFIB can be used to mill a sample area on the order of 5-500 μm2 using a beam having a current in the range of 1-1000 nA. Thus, the sputtering rate in PFIB is relatively high. However, FIB and PFIB techniques are generally insufficient for planar delayering for micromachining purposes, because of limitations in achieving nanometer scale roughness and planarity when treating different materials in the same sample.
Broad ion beam (BIB) techniques can be used for planar polishing and/or to mill a sample area on a millimeter scale. Beam currents in BIB tend to be in the range of 1000-20,000 nA. However, BIB generally lacks real-time control and site-specific (e.g., target alignment and beam precision) capabilities. Even more broadly, general polishing and RIE are inefficient, not site-specific, and generally require intermittent external microscope observations to determine progress.
No techniques are known to the inventors that provide site-specific planar delayering solutions at the wafer level. Thus, there is generally a lack of efficient, controlled and reliable site-specific delayering techniques and tools for advanced 45-10 nm nodes in semiconductor and/or integrated circuit metrology and/or failure analysis. A need is felt for such a technique and/or tool.
This “Discussion of the Background” section is provided for background information only. The statements in this “Discussion of the Background” are not an admission that the subject matter disclosed in this “Discussion of the Background” section constitutes prior art to the present disclosure, and no part of this “Discussion of the Background” section may be used as an admission that any part of this application, including this “Discussion of the Background” section, constitutes prior art to the present disclosure.